1. Technical Field
This disclosure relates generally to processors, and, more specifically, to interfacing processors with memory.
2. Description of the Related Art
When data is transmitted between a processor and memory, a data strobe signal (sometimes referred to as DQS) is provided with the data signal to indicate when voltages on the bus correspond to actual data values and to coordinate the capturing of the data values from the bus. In a write operation, the memory controller interface on the processor is responsible for generating the data strobe signal for the data being written to memory. In a read operation, memory generates the data strobe signal for the data being read.
The data strobe signal is typically transmitted over the same bidirectional bus line. As such, the DQS signal line may be permitted to float (i.e., operate in a tri-state) between performances of read and write operations. If the recipient attempts to capture data before the data strobe signal is valid, the tri-stated value of the signal line may cause data to be captured incorrectly. Still further, if the recipient starts capturing data after an initial cycle of the DQS signal, not all of the data will be captured.